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ASAHI KASEI
[AK2540]
AK2540 Quad T1 Transceiver
FEATURE - 4ch short haul T1 transceiver with jitter attenuator - Jitter Tolerance: Compliant with GR-499 Category I,II and TR 62411 - Transmitter Pulse Shape: Compliant with GR-499 and ANSI T1.102 (1993) - Loss of Signal Detection - Local/Remote Loopback Mode - Driver Failure Monitor - Current limiter in transmit drivers for short circuits protection - Hardware/Host Control Mode - Single 3.3V5% or 5.0V5% Operation - Low Power Consumption - Package: 144LQFP BLOCK DIAGRAM
TRANSCEIVER 1
Remote Loopback Local Loopback
TCLK1 TPOS1 TNEG1
DFM
PULSE SHAPER
DFM1
TTIP1 TRING1
TAOS
JITTER ATT
RCLK1 RPOS1 RNEG1
CLOCK &DATA RECOVERY LOS
RTIP1 RRING1 LOS1
RCLK2-4 RPOS2-4 RNEG2-4 TCLK2-4 TPOS2-4 TNEG2-4
TRANSCEIVER 2-4
DFM2-4 TTIP2-4 TRING2-4 RTIP2-4 RRING2-4 LOS2-4 MCLK
CONTROL
CLKGEN
MCLKSEL
Quad T1 Transceiver Block Diagram
MS0012-E-00
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ASAHI KASEI
[AK2540]
GENERAL DESCRIPTIONS The AK2540 is the quad short haul T1 transceiver for asynchronous applications, such as M13 MUX, etc. It includes Transmitter, Clock and Data Recovery, Jitter Attenuator, LOS Detector, Driver Failure Monitor, Control Circuits, etc. in one LQFP-144 package. Internally generated transmit pulse provides the appropriate pulse shape for line length ranging from 0 to 655 feet from a DSX-1 cross connect.
PIN ASSIGNMENTS
MS0012-E-00
NC R/W(WR)_LENG03 AS(ALE)_LENG24 DS(RD)_LENG14 CS_LENG04 BTS_AIS1SEL INT_LOMC HWMODE RESET SEL5V CLKE TEST8 RRING4 RTIP4 TEST7 TEST6 RRING3 RTIP3 TEST5 PVSS NC MCLK MCLKSEL PVDD BVDD BGREF BVSS TEST4 RRING2 RTIP2 TEST3 TEST2 RRING1 RTIP1 TEST1 NC
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
DFM3 AIS3 TPOS3 TNEG3 TCLK3 LOS3 RPOS3 RNEG3 NC RCLK3 DFM4 AIS4 TAVDD1 NC TAVSS1 TPOS4 TNEG4 TCLK4 LOS4 RPOS4 RNEG4 RCLK4 DAVSS2 NC IOVDD IOVSS NC NC AD0_LENG21 AD1_LENG11 AD2_LENG01 AD3_LENG22 AD4_LENG12 AD5_LENG02 AD6_LENG23 AD7_LENG13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
NC NC NC LLOOP4 RLOOP4 TTIP4 TVSS4 TVDD4 TRING4 AVSS4 NC LLOOP3 RLOOP3 TTIP3 TVSS3 TVDD3 TRING3 AVSS3 NC LLOOP2 RLOOP2 TTIP2 TVSS2 TVDD2 TRING2 AVSS2 NC NC LLOOP1 RLOOP1 TTIP1 TVSS1 TVDD1 TRING1 AVSS1 NC
(TOP VIEW)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
DFM1 AIS1 TPOS1 TNEG1 TCLK1 LOS1 RPOS1 RNEG1 NC RCLK1 DFM2 AIS2 NC NC TAVDD2 TAVSS2 NC DVSS DVDD DAVSS1 NC TPOS2 TNEG2 TCLK2 NC LOS2 RPOS2 RNEG2 RCLK2 NC JASELT JASELR NC RAVDD RAVSS NC
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ASAHI KASEI
[AK2540]
PIN CONDITION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Name DFM3 AIS3 TPOS3 TNEG3 TCLK3 LOS3 RPOS3 RNEG3 NC RCLK3 DFM4 AIS4 TAVDD1 NC TAVSS1 TPOS4 TNEG4 TCLK4 LOS4 RPOS4 RNEG4 RCLK4 DAVSS2 NC IOVDD IOVSS NC NC AD0_LENG21 AD1_LENG11 AD2_LENG01 AD3_LENG22 AD4_LENG12 AD5_LENG02 AD6_LENG23 AD7_LENG13
I/O O I I I I O O O O O I I I I I I O O O O I I I
Pin Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power
AC Load 15pF
DC Load
Comments Note2)
15pF 15pF 15pF 15pF 15pF Note2)
15pF 15pF 15pF 15pF
I/O I/O I/O I/O I/O I/O I/O I/O
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
50pF 50pF 50pF 50pF 50pF 50pF 50pF 50pF
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ASAHI KASEI
[AK2540]
Pin # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Pin Name NC R/W(WR)_LENG03 AS(ALE)_LENG24 DS(RD)_LENG14 CS_LENG04 BTS_AIS1SEL INT_LOMC HWMODE RESET SEL5V CLKE TEST8 RRING4 RTIP4 TESE7 TEST6 RRING3 RTIP3 TEST5 PVSS NC MCLK MCLKSEL PVDD BVDD BGREF BVSS TEST4 RRING2 RTIP2 TEST3 TEST2 RRING1 RTIP1 TEST1 NC
I/O I I I I I O I I I I I I I I I I I I I I I I I O I I I I I I I I I
Pin Type CMOS CMOS CMOS CMOS CMOS Open drain CMOS CMOS CMOS CMOS CMOS Analog Analog CMOS CMOS Analog Analog CMOS Power CMOS CMOS Power Power Analog Power CMOS Analog Analog CMOS CMOS Analog Analog CMOS
AC Load
DC Load
Comments
PMOS Open drain
Note1)
Note1) Note1)
Note1)
12k
1% accuracy Note1)
Note1) Note1)
Note1)
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ASAHI KASEI
[AK2540]
Pin # 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Pin Name NC RAVSS RAVDD NC JASELR JASELT NC RCLK2 RNEG2 RPOS2 LOS2 NC TCLK2 TNEG2 TPOS2 NC DAVSS1 DVDD DVSS NC TAVSS2 TAVDD2 NC NC AIS2 DFM2 RCLK1 NC RNEG1 RPOS1 LOS1 TCLK1 TNEG1 TPOS1 AIS1 DFM1
I/O I I I I O O O I I I I I I I I I
Pin Type Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power Power Power
AC Load
DC Load
Comments
Note2) Note2) 15pF 15pF 15pF 15pF
I O O O O O I I I I O
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS 15pF 15pF 15pF 15pF 15pF 15pF
Note2)
Note2)
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[AK2540]
Pin # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Pin Name NC AVSS1 TRING1 TVDD1 TVSS1 TTIP1 RLOOP1 LLOOP1 NC NC AVSS2 TRING2 TVDD2 TVSS2 TTIP2 RLOOP2 LLOOP2 NC AVSS3 TRING3 TVDD3 TVSS3 TTIP3 RLOOP3 LLOOP3 NC AVSS4 TRING4 TVDD4 TVSS4 TTIP4 RLOOP4 LLOOP4 NC NC NC
I/O I O I I O I I
Pin Type Power Analog Power Power Analog CMOS CMOS
AC Load
DC Load
Comments
driver output
driver output Note2) Note2)
I O I I O I I I O I I O I I I O I I O I I
Power Analog Power Power Analog CMOS CMOS Power Analog Power Power Analog CMOS CMOS Power Analog Power Power Analog CMOS CMOS driver output Note2) Note2) driver output driver output Note2) Note2) driver output driver output Note2) Note2) driver output
Note1 )Should be connected to VSS externally. Note2 )Should be connected to VSS externally in host mode. Note3 )All NC pins are recommended to connected to VSS externally. MS0012-E-00 6 2000/1
ASAHI KASEI PIN DESCRIPTIONS
Pin Name T1 Transceiver TTIP1-4 TRING1-4 TPOS1-4 TNEG1-4 TCLK1-4 RTIP1-4 RRING1-4 RPOS1-4 RNEG1-4 RCLK1-4 RLOOP1-4 LLOOP1-4 LENG01-04 LENG11-14 LENG21-24 AIS1-4 AIS1SEL JASELR JASELT DFM1-4 LOS1-4 O O I I I I I O O O I I I I I I I I I O O Transmit Tip/Ring Output pins Bipolar output over transmit transformer Transmit Positive/Negative Data Input pins Input on the falling edge of TCLK Transmit Clock Input pins Receive Tip/Ring Input pins Bipolar Input over receive transformer Receive Positive/Negative Data Output pins Output on the rising/falling edge of RCLK (determined by CLKE pin) Receive Clock Output recovered from receive data input pins Remote Loopback Control input pins Local Loopback Control input pins Line Length Control 0 input pins Line Length Control 1 input pins Line Length Control 2 input pins Transmit AIS Enable input pins Transmit All Ones/Zero Selection input pins when AIS is enabled Jitter Attenuator Select input pin, placed at Receiver Jitter Attenuator Select input pin, placed at Transmitter Driver Failure Monitor output pins Loss of signal output pins Output "high" when detect loss of signal LOSx output is not masked by MLOSx register. Positive Power Supply for the Transmit Driver Negative Power Supply for the Transmit Driver Analog ground. I O 1.544MHz or 24.704MHz External Reference Clock input pin Loss of master clock output pin. Output "high" when detect loss of master clock LOMC output is not masked by MLOMC register. AS(ALE) INT I O Address Select(Address Latch Enable) input pin Interrupt Output pin(PMOS open drain), Active High, INT output goes "high" when the alarm is reported to any one of LOSx, LOTCx or LOMC registers. This pin can be masked by MLOSx, MLOTCx or MLOMC registers. DS(RD) R/W (WR) I I Data Strobe(Read Enable) input pin Read/Write(Write Enable) input pin I/O Function
[AK2540]
Comments
Note1) Note1) Note1) Note1) Note1) Note1) Note1) Note1) Note1)
TVDD1-4 TVSS1-4 AVSS1-4 Common Block MCLK LOMC
Note1)
Note2) Note2)
Note2) Note2)
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ASAHI KASEI
[AK2540]
Pin Name CS BTS
I/O I I Chip Select input pin Bus Type Select input pin BTS="H" : Motorola Mode BTS="L" : Intel Mode
Function
Comments Note2) Note2)
Common block (Cont.)
AD0-AD7 MCLKSEL
I/O I
Address/Data Input/Output pins Used for read/write internal registers. MCLK Select input pin CLKSEL="H":1.544MHz CLKSEL="L":24.704MHz
Note2)
HWMODE
I
Hardware/ Host Mode Select input pin HWMODE="H": Hardware Mode HWMODE="L": Host Mode
SEL5V
I
5.0V /3.3V VDD Select input pin SEL5V="H": 5V operation SEL5V="L": 3.3V operation
CLKE RESET
I I
RCLK clock edge select input pin Reset Input pin Active "High" input pulse over 200ns initializes the internal circuit and forces RPOSx/RNEGx output "low" and LOSx output "high".
TEST1 - 8 TAVDD1,2 TAVSS1,2 RAVDD RAVSS DVDD DVSS DAVSS1,2 IOVDD IOVSS BVDD BVSS PVDD PVSS BGREF
I
Factory Use. Should be connected to "VSS" externally. Positive Power Supply for the analog circuitry in the transmitters Negative Power Supply for the analog circuitry in the transmitters Positive Power Supply for the digital circuitry in the transmitters Negative Power Supply for the digital circuitry in the transmitters Positive Power Supply for Digital Negative Power Supply for Digital Ground for Digital Positive Power Supply for I/O Negative Power Supply for I/O Positive Power Supply for Reference Circuit Negative Power Supply for Reference Circuit Positive Power Supply for PLL Negative Power Supply for PLL Bandgap Reference Output pin 12k1% external register should be connected across this pin and VSS.
Note1) Hardware Mode Note2) Host Mode
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ASAHI KASEI ABSOLUTE MAXIMUM RATINGS
Parameter DC Supply Input Voltage Symbol VDD VIN1 VIN2 Input Current Storage Temperature IIN Tstg -55 Min -0.3 -0.3 -3.2 Typ Max 6.5 VDD+0.3 VDD+0.3 10 130 Units V V V mA C
[AK2540]
Conditions
Apply to except for RTIPx, RRINGx Apply to RTIPx,RRINGx All Pins
RECOMMENDED OPERATING COMDITIONS
Parameter DC Supply 1 DC Supply 2 Ambient Operating Temperature Symbol V+1 V+2 Ta min 3.135 4.75 -40 typ 3.3 5.0 25 max 3.465 5.25 +85 Units V V C Conditions 3.3V 5% 5.0V 5%
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Parameter Power Consumption(/ch) Power Consumption(/ch) Digital High-Level Output Voltage Digital Low-Level Output Voltage Digital High-Level Input Voltage Digital Low-Level Input Voltage Input Leak Current Output Current (VOH=VDD-0.5) Symbol PD PD VOH VOL VIH VIL Ii IOH 2.0 0.7VDD 0.3VDD 10 0.9VDD 0.4 min typ 106 130 max 260 280 Units Conditions mW Note1 mW Note2 V V V V A mA INT pin PMOS Open Drain IOH=-500A IOL=500A
Note 1: typ: 50% mark, Room temp., VDD 3.3V, line length 399feet, Load 100ohm max: 100% mark, Temp./VDD in all range, line length 655feet, Load 100ohm Any other loads (ex. external pull up register, etc.) is not included except lines. Note 2: typ: 50% mark, Room temp., VDD 5.0V, line length 399feet, Load 100ohm max: 100% mark, Temp./VDD in all range, line length 655feet, Load 100ohm Any other loads (ex. external pull up register, etc.) is not included except lines.
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ASAHI KASEI
[AK2540]
RECEIVER Receiver characteristics are guaranteed under the conditions shown below. VDD=3.3V5% or 5.0V5%, VSS=0V, GND=0V, Ta=-40 - 85C, MCLK frequency: 1.544MHz100ppm, 24.704MHz100ppm, AMI input data rate:1.544bps130ppm(reference input level: 3V0p20%)
Parameter Sensitivity Loss of Signal Threshold Jitter Tolerance Consecutive Zeros before Loss of Signal Input Impedance Symbol Min -6 0.35 170 20 0.5 175 0.7 180 Typ Max Units dB V0p Conditions Note 1 Note 2 Note 3 kohm Note 4
GR-499 CategoryI,II, ATT TR 62411
Note 1: Relative value to the reference level. Compare at 772kHz with all mark pattern. Note 2: Level at the line side of transformer. Loss of signal is logical OR between an analog loss of signal, which monitors input level, and a digital loss of signal, which checks recovered data stream. Note 3: The device will tolerate consecutive zeros until loss of signal is reported with QRSS (PN20 Modified) pattern. Note 4: It is not subject to be tested for the production. Guaranteed by design.
JITTER TOLERANCE
JITTER TOLERANCE 1000 100 10 1 0.1 1 10 100 1000 10000 100000 Jiiter Frequency(Hz)
TR62411
MS0012-E-00
Jitter Amplitude(UIpp)
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ASAHI KASEI
[AK2540]
TRANSMITTER Transmitter characteristics are guaranteed under the conditions shown below. VDD=3.3V5% or 5.0V5%, VSS=0V, GND=0V, Ta=-40 - 85C, MCLK frequency: 1.544MHz100ppm, 24.704MHz100ppm
Parameter Output Pulse Shape Output Pulse Amplitude Output Pulse Imbalance Output Jitter 10Hz-8kHz 10Hz-40kHz 8kHz-40kHz Broad Band Power Levels @772kHz Power Levels @1.544MHz Consecutive Zeros before DPM Alarm Note 1: Measured at the DSX terminated with 100ohm. Note 2: Turns Ratio and DCR of transmission transformer are recommended value. Note 3: Measured in a 2kHz bandwidth about the specified frequency. Transmit all mark pattern. Note 4: Referenced to the power at 772kHz. 320 12.6 15 2.5 3.0 3.5 0.4 0.02 0.025 0.025 0.05 17.9 -29 dBm Note3 dB Note3, Note4 V0p dB UIpp Symbol Min Typ Max Units Conditions
GR-499,Note1
Note1, Note2
ISOLATED PULSE MASK (GR-499)
Normalized Amplitude 1.5 1 0.5 0 -0.5 -1 -1 -0.5 0 0.5 1 1.5 Time, in Unit Intervals
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ASAHI KASEI
[AK2540]
JITTER ATTENUATOR Jitter Attenuator characteristics are guaranteed under the conditions shown below. VDD=3.3V5% or 5.0V5%, VSS=0V, GND=0V, Ta=-40 - 85C, MCLK frequency: 1.544MHz100ppm, 24.704MHz100ppm
Parameter Jitter attenuator curve corner frequency Jitter attenuation @ 10kHz Attenuator input jitter tolerance before FIFO overflow/underflow protection Intrinsic Jitter 0.03 0.06 UIpp Symbol Min Typ 6 50 43 Max Units Hz dB UIpp Input Jitter: 1 UIpp Conditions
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ASAHI KASEI
[AK2540]
AC CHARACTERISTICS(Clock/Data)
Parameter Clock Frequency Clock Pulse Width MCLK1 MCLK2 MCLK1 MCLK2 Clock Pulse Width Clock Pulse Width Duty Cycle Setup/Hold Time TCLK RCLK RCLK TCLK RCLK RPOS RNEG Setup/Hold Time TCLK TPOS TNEG Rise Time RCLK, TCLK RPOS, TOPS RNEG, TNEG Fall Time RCLK, TCLK RPOS, TPOS RNEG, TNEG Note 1: All AK2540 specifications are to be within the limit with 100ppm MCLK. However, MCLK needs to be within 32ppm range in order to transmit AIS of 32 ppm accuracy during the loss of TCLK. Note 2: Duty Cycle:(tpwho/( tpwho + tpwlo)) x 100% Note 3: Drive 15pF Load Capacitance tf 50 ns Refer to Fig.3 Note3 tr 50 ns Refer to Fig.3 Note3 tsu2 th2 50 ns Refer to Fig.2 tsu1 th1 150 ns tpwhi tpwli tpwho tpwlo 50 % 324 ns Refer to Fig.1 Note 3 Note 2 Note 3 Refer to Fig.1 Symbol fci1 fci2 tpwhi tpwli 20 324 ns ns Min Typ Max Units Conditions MHz 100ppm Note 1 ns Refer to Fig.4 1.544MHz Refer to Fig.4 24.704MHz Refer to Fig.2
1.543846 1.544000 1.544154 24.70153 24.70400 24.70647 324
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ASAHI KASEI
[AK2540]
tpwho 50%
tpwlo 50% tsur 50% thr tsur 50% When CLKE=0 50% thr
RCLK
RPOS/RNEG
50% When CLKE = 1 Fig. 1 Receiver Timing
tpwhi
tpwli
TCLK
50% tsut 50%
50% tht
50%
TPOS/TNEG
Fig. 2 Transmitter Timing
tr 90% 10% 90%
tf
10%
Fig. 3 Rise and Fall Times (RCLK,RPOS,RNEG,TCLK,TPOS,TNEG,) tpwhi 50% tpwli 50% 50%
MCLK
Fig.4 Master Clock Timing
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ASAHI KASEI
[AK2540]
AC CHARACTERISTICS(Parallel Port)
Parameter Motrola Mode Address Setup Time Address Hold Time ASDS Delay Time DSAS Delay Time Read Data Delay Time Read Data Hold Time R/W Setup Time R/W Hold Time CS Setup Time CS Hold Time Write Data Setup Time Write Data Hold Time DS Pulse Width AS Pulse Width Address InvalidDS Delay Time Intel Mode Address Setup Time Address Hold Time ALEWR Delay Time WRALE Delay Time RDALE Delay Time Read Data Delay Time Read Data Hold Time CS Setup Time CS Hold Time Write Data Setup Time Write Data Hold Time RD Pulse Width WR Pulse Width ALE Pulse Width Address InvalidRD Delay Time t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 10 10 20 20 20 10 15 40 20 100 100 20 10 40 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 10 10 20 20 10 10 10 15 40 20 100 20 10 40 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Min Typ Max Units Conditions
Notes: CL= 50pF on AD0-AD7. All of the timing is specified at 50%VDD.
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ASAHI KASEI
[AK2540]
Motorola Mode(READ) CS t9 t13 t14 AS t5 t10
DS
t4 t6
t1
t2 t15 Data
AD7-0 R/W
Address
t7
t8
Motorola Mode(WRITE) t9 t13 DS t14 AS t3 t4 t10
CS
t1
t2
t11 Data t7
t12
AD7-0 R/W
Address
t8
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ASAHI KASEI
[AK2540]
Intel Mode(READ) CS
t28
t29
WR t34 ALE t21 AD7-0 RD t22 Data t35 t32 t27 t26 t25
Address
Intel Mode(WRITE)
CS
t28 t33 t34 t23
t29
WR
t24
ALE t21 AD7-0 RD t22 t30 Data t31
Address
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ASAHI KASEI THEORY OF OPERATION
[AK2540]
Mode of Operation There are two mode of operation as selected by HWMODE pin. One is the hardware mode and the other is the host mode. The device is in the hardware mode when HWMODE pin is pulled high and in the host mode when HWMODE pin is pulled low. Minimum information is available in hardware mode. In Hardware Mode, the device is controlled by the appropriate pins. In Host Mode, the device is controlled by appropriate registers described after through parallel interface. In Host Mode, all interrupt can be masked by appropriate mask register. However, the status registers and hard flag pins show the current status regardless of the mask register setting. Pulse Shape Control (Hardware Mode and Host Mode) In Hardware Mode, the transmit pulse shape in channel x (x = 1,2,3 and 4) is determined by Line Length control pins LENG0x through LENG2x as shown in Table 1. Table 1. Line Length Control LENG2x 0 0 0 0 1 1 1 1 X=1,2,3 and 4 In Host Mode, the transmission pulse shape is determined by appropriate register described in the Register Description section later LENG1x 0 0 1 1 0 0 1 1 LENG0x 0 1 0 1 0 1 0 1 Line Length Reserved 0-133feet 133-266feet 266-399feet 399-533feet 533-655feet Reserved Reserved
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ASAHI KASEI
[AK2540]
Jitter Attenuator (Hardware Mode and Host Mode) Jitter Attenuator may be placed either transmitter path or receiver path, or bypassed according to JASELR and JASELT both in Hardware Mode and Host Mode as described in table 2. Jitter Attenuators are to be placed at the same place in channel 1 through channel 4. Table 2. Jitter Attenuator Place Selection JASELR 0 0 1 1 JASELT 0 1 0 1 Location of Jitter Attenuator Bypassed Transmitter Receiver Reserved (NA)
AIS (Hardware Mode and Host Mode) AIS in channel x is selected when AISx is "high". In AIS mode the TPOS and TNEG inputs are ignored, but the transmitter remains locked to the TCLK input. AIS can be enabled simultaneously with Local Loopback. AIS overdrives Remote Loopback. In this mode, either all ones or all zeros are transmitted according to the AIS1SEL selection. (see table 3) Table 3. AIS Control AISx 0 0 1 1 AIS1SEL 0 1 0 1 X=1,2,3 and 4 TTIP/TRING Normal Normal All "0" All "1"
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ASAHI KASEI
[AK2540]
Loopbacks (Hardware Mode and Host Mode) Local Loopback (LLOOP) in channel x is selected when LLOOPx is "high" and RLOOPx is "low". In LLOOP mode, the receiver circuits are inhibited. The transmitter circuits are unaffected by LLOOP. Remote Loopback (RLOOP) in channel x is selected when RLOOPx is "high" and LLOOPx is "low". However, RLOOP is ignored if AIS is selected. In RLOOP mode, the transmit clock and data inputs (TCLK and TPOS/TNEG) are ignored. The RPOS/RNEG outputs are looped back to the transmit circuits and output on TTIP and TRING at the RCLK frequency. Receiver circuits are unaffected by the RLOOP and continue to output the data and clock signals received from the line. Table 4. Loopback mode Selection RLOOPx 0 0 1 1 LLOOPx 0 1 0 1 Function Normal Local Loop back Remote Loop back Reserved (NA) The transmit clock and data inputs (TCLK and TOPS/TNEG) are looped back and output at RCLK and RPOS/RNEG.
Driver Performance Monitor (Host Mode) The device incorporates an internal Driver Performance Monitor (DPM) in parallel with TTIP and TRING. DPMx is set "high" when DPM detect 320 bits of consecutive space in channel x. INT pin becomes "high" when DPMx is set "high", if MDPMx is "low". DPMx registers represent the current status regardless of the MDPMx status. DPMx returns to "low", when a mark is detected. However, DPMx is to be kept "high" for 320 TCLK cycle after the first detection of the event. DPM output is ignored when all "0" AIS is being transmitted Line Short Protection Circuit The transmit driver includes a line short protection circuit. When the line short protection circuit detect a line short, transmit signal is fixed to "space". The line short protection circuit monitor the line short every 160bits cycle. (This alarm is not outputted. Line short is shown for Driver Failure described below.)
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ASAHI KASEI
[AK2540]
Driver Failure Monitor (Hardware Mode and Host Mode) Driver Failure Monitor asserts the detection of consecutive space or line short. When DPMx is set "high" or line short circuit in channel x is detected, DFMx(Driver Failure Monitor) register is set "high" and DFMx pin becomes "high". INT pin becomes "high" when DFMx is set "high" if MDFMx is "low". DFMx registers and DFMx pins represent the current status regardless of the MDFMx status.
Loss of signal (Hardware Mode and Host Mode) The receiver will indicate loss of signal upon receiving 175 consecutive zeros (DLOS) or detecting input level being below the threshold (ALOS). LOSx returns to "low" when the received signal returns to 12.5% ones density and not including 100 consecutive zeros. (GR-820) When Loss of Signal is detected in channel x, LOSx register is set "high" and LOSx pin becomes "high". When LOSx is set "high", interrupt will be issued on INT pin if MLOSx is "low". LOSx pin becomes high regardless of MLOSx status. MLOSx is active-high and masks LOSx interrupt. LOSx registers and LOSx pins represent the current status of received signal regardless of the MLOSx status. There are also ALOSx registers and the current status of each channel is available.
Loss of TCLK (Host Mode Only) Loss of TCLKx is reported by setting LOTCx "high". When LOTCx is set "high", INT output becomes "high" if MLOTCx is "low". MLOTCx is active-high and masks LOTCx interrupt. LOTCx represents the current status of TCLKx and can be read regardless of MLOTCx status. When Loss of TCLKx is detected, TTIPx/TRINGx will be forced to "0"(except Remote loopback and AIS), and AIS in channel x is sent synchronized with MCLK if AISx is selected. INT_LOMC output (Hardware Mode and Host Mode) In Host Mode, INT_LOMC(Interrupt Output) output becomes "high" when the alarm is reported at any one of ALOSx, LOSx, LOTCx, DFMx or DPMx registers. MALOSx, MLOSx, MLOTCx, MDFM or MDPM registers. In Hardware Mode, INT_LOMC pin assert LOMC(Loss of MCLK alarm). INT_LOMC pin can be masked by
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ASAHI KASEI REGISTER DESCRIPTIONS
[AK2540]
REGISTER MAP
*A7-A4="0" Address
A3 A2 A1 A0
Bit7 Bit6 Bit5
Function
Bit4 Bit3 Bit2 Bit1 Bit0
Status Register (READ ONLY)
0 0 0
0 0 0
0 0 1
0 1 0
DPM4 (0) LOTC4 (1) ALOS4 (1)
DPM3 (0) LOTC3 (1) ALOS3 (1) MDPM3 (1) MLOTC3 (1) MALOS3 (1) MSK3 (1) LENG11 (0) LENG12 (0) LENG13 (0) LENG14 (0) JASELT (0)
DPM2 (0) LOTC2 (1) ALOS2 (1) MDPM2 (1) MLOTC2 (1) MALOS2 (1) MSK2 (1) LENG01 (1) LENG02 (1) LENG03 (1) LENG04 (1) POL (1)
DPM1 (0) LOTC1 (1) ALOS1 (1) MDPM1 (1) MLOTC1 (1) MALOS1 (1) MSK1 (1) RLOOP1 (0) RLOOP2 (0) RLOOP3 (0) RLOOP4 (0) RDEN (0)
DFM4 (0) LOS4 (1) MDFM4 (1) MLOS4
DFM3 (0) LOS3 (1) MDFM3 (1) MLOS3
DFM2 (0) LOS2 (1) MDFM2 (1) MLOS2
DFM1 (0) LOMC (1) LOS1 (1) MDFM1 (1) MLOS1
Mask Control Register (WRITE/READ)
0 0 0 0
0 1 1 1
1 0 0 1
1 0 1 0
MDPM4 (1) MLOTC4 (1) MALOS4 (1) MSK4 (1)
(1) -
(1) -
(1) -
(1) MLOMC (1)
Channel Control Register (WRITE/READ)
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
LENG21 (0) LENG22 (0) LENG23 (0) LENG24 (0)
LLOOP1 (0) LLOOP2 (0) LLOOP3 (0) LLOOP4 (0) AIS1SEL (1)
AIS1 (0) AIS2 (0) AIS3 (0) AIS4 (0) -
-
PD1 (1) PD2 (1) PD3 (1) PD4 (1)
Global Control Register (WRITE/READ)
1
0
1
1
JASELR (0)
-
-
* The other addresses are reserved. * Initial value is in ( ). * "<>" shows I/O pin name. Address A0-A3 should be input via AD0-AD3 pins.
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ASAHI KASEI
[AK2540]
STATUS REGISTER
Symbol LOSx (x=1 to 4) LOTCx (x=1 to 4) DPMx (x=1 to 4) DFMx (x=1 to 4) ALOSx (x=1 to 4) LOMC Description Loss of signal alarm for channel x. Read only register. When the loss of signal is detected, LOSx is set High. Loss of TCLK alarm for channel x. Read only register. When the loss of TCLKx is detected, LOTCx is set High. Driver Performance Monitor alarm for channel x. Read only register. When 320 bits of consecutive space is detected in channel x, DPMx is set high. Driver Failure Monitor alarm for channel x. Read only register. When DPM or short circuit is detected in channel x , DFMx is set high. Analog loss of signal alarm for channel x. Read only register. When the analog loss of signal is detected, ALOSx is set High. Loss of MCLK alarm. Read only register. When the loss of MCLK is detected, LOMC is set High.
MASK CONTROL REGISTER Symbol MLOSx (x=1 to 4) Description Mask loss of signal alarm for channel x (LOSx). MLOSx is active-high and prevents LOSx from setting INT output "high". LOSx register can be read regardless of the MLOSx status. Initial value is "high". Mask loss of TCLK alarm for channel x (LOTCx). MLOTCx is active high and prevents LOTCx from setting INT output "high". LOTCx register can be read regardless of the MLOTCx status. Initial value is "high". Mask DPM alarm for channel x (DPMx). MDPMx is active high Initial value is "high". Mask DFM alarm for channel x (DFMx). MDFMx is active high Initial value is "high". MSKx is active-high and prevents LOSx, LOTCx, DFMx and DPMx in channel x from setting INT output "high". Initial value is "high". Mask analog loss of signal alarm for channel x (ALOSx). MALOSx is active-high and prevents ALOSx from setting INT output "high". ALOSx register can be read regardless of the MALOSx status. Initial value is "high". Mask loss of MCLK alarm (LOMC). MLOMC is active high and prevents LOMC from setting INT output "high". LOMC register can be read regardless of the MLOMC status. Initial value is "high".
MLOTCx (x=1 to 4)
MDPMx (x=1 to 4) MDFMx (x=1 to 4) MSKx (x=1 to 4) MALOSx (x=1 to 4)
MLOMC
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ASAHI KASEI
[AK2540]
CHANNEL CONTROL REGISTER
Symbol LENGyx Description The generated transmit pulse in channel x provides the appropriate pulse shape for line length from a DSX-1 cross connect through the setting of this register as shown below in Table 5. Loopback mode of channel x is activated through the setting of these registers as shown below in Table 6. AISx is active-high to transmit AIS in the corresponding channel. PDx is active-high to set the corresponding transceiver in power down mode. TTIPx and TRINGx goes "low". LOSx goes "high" in power down mode. Initial value is "high".
RLOOPx/ LLOOPx AISx PDx
GLOBAL CONTROL REGISTER
Symbol JASELR/JA SELT POL RDEN Description Jitter Attenuator is placed by these resisters as shown is Table 7. Initial values are "low" This register as shown in Table 8 controls TIP/RING output polarity. Initial value is "high". RDEN is active-high and enabling RCLK, RPOS, and RNEG output upon Loss of signal. RCLK, RPOS and RNEG are forced to "high" or "low" upon Loss of Signal when RDEN is "low". (Please refer to output control) Initial value is "low". All mark is transmitted as AIS when AIS1SEL is "high". transmitted as AIS when AIS1SEL is "low". All space is
AIS1SEL
Table 5. Line Length Control LENG2x 0 0 0 0 1 1 1 1 LENG1x 0 0 1 1 0 0 1 1 LENG0x 0 1 0 1 0 1 0 1 Line Length Reserved 0-133feet 133-266feet 266-399feet 399-533feet 533-655feet Reserved Reserved
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ASAHI KASEI Table 6. Loopback mode Selection RLOOPx 0 0 1 1 LLOOPx 0 1 0 1 Function Normal (Initial value) Local Loop back Remote Loop back Reserved (NA)
[AK2540]
Table 7. Jitter Attenuator Place Selection JASELR 0 0 1 1 JASELT 0 1 0 1 Location of Jitter Attenuator Bypassed (Initial value) Transmitter Receiver Reserved (NA)
Table 8. TIPx/RINGx Polarity Control POL 1 0 POSx/NEGx 0 1 0 1 TIPx/RINGx space mark mark space
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ASAHI KASEI
[AK2540]
OUTPUT CONTROL * : don't care LOS: LOSx output and LOSx register
Reset, Loss of MCLK, Power down (Host Mode)
RESET MCLK PD Loopback Local 1 0 0 0 0 0 0 0 0 * loss loss clocked clocked clocked clocked clocked clocked * * * 1 1 1 1 1 1 * * * * * * * * * Remote * * * * * * * * * * 1 0 1 1 1 0 0 0 * * * 0 1 1 0 1 1 * * * * 0 1 * 0 1 POL RDEN CLKE TTIP TRING High-Z(Note1) 0 0 High-Z(Note1) High-Z(Note1) High-Z(Note1) High-Z(Note1) High-Z(Note1) High-Z(Note1) 0 0 0 0 0 1 0 0 1 RCLK RPOS RNEG 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 LOS DFM
Reset, Loss of MCLK (Hardware Mode)
RESET MCLK Loopback Local 1 0 * loss * * Remote * * * * CLKE TTIP TRING 0 0 0 0 RCLK RPOS RNEG 0 0 1 1 0 0 LOS DFM
In Hardware Mode, POL is fixed to "1" and RDEN is fixed to "0".
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ASAHI KASEI
[AK2540]
Normal Operation(RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=RLOOP=0)
POL 1 1 1 1 1 1 0 0 0 0 0 0 RDEN * 0 * 0 1 1 * 0 * 0 1 1 TCLK clocked clocked loss loss clocked loss clocked clocked loss loss clocked loss Receive signal clocked loss clocked loss loss loss clocked loss clocked loss loss loss TTIP TRING TPOS TNEG TPOS TNEG 0 0 TPOS TNEG 0 TPOS TNEG TPOS TNEG 0 0 TPOS TNEG 0
RCLK RCLK RCLK RCLK RCLK
RCLK
RPOS RNEG RTIP RRING 0 RTIP RRING 0 RTIP RRING RTIP RRING RTIP RRING 1 RTIP RRING 1 RTIP RRING RTIP RRING
LOS 0 1 0 1 1 1 0 1 0 1 1 1
DFM active active 0 0 active 0 active active 0 0 active 0
0
0
RCLK
RCLK
0
0
RCLK
Normal Operation: Transmit all space (RESET=0, AIS=1,AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=RLOOP=0)
POL 1 1 1 1 1 1 0 0 0 0 0 0 RDEN * 0 * 0 1 1 * 0 * 0 1 1 TCLK clocked clocked loss loss clocked loss clocked clocked loss loss clocked loss Receive signal clocked loss clocked loss loss loss clocked loss clocked loss loss loss TTIP TRING 0 0 0 0 0 0 0 0 0 0 0 0
RCLK
RCLK
RPOS RNEG RTIP RRING 0 RTIP RRING 0 RTIP RRING RTIP RRING RTIP RRING 1 RTIP RRING 1 RTIP RRING RTIP RRING
LOS 0 1 0 1 1 1 0 1 0 1 1 1
DFM 0 0 0 0 0 0 0 0 0 0 0 0
0
RCLK
0
RCLK
RCLK
RCLK
0
RCLK
0
RCLK
RCLK
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ASAHI KASEI
[AK2540]
Normal Operation: Transmit all mark (RESET=0, AIS=1,AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=RLOOP=0)
POL 1 1 1 1 1 1 0 0 0 0 0 0 RDEN * 0 * 0 1 1 * 0 * 0 1 1 TCLK clocked clocked loss loss clocked loss clocked clocked loss loss clocked loss Receive signal clocked loss clocked loss loss loss clocked loss clocked loss loss loss TTIP TRING All Mark All Mark All Mark (Note2) All Mark (Note2) All Mark All Mark (Note2) All Mark All Mark All Mark (Note2) All Mark (Note2) All Mark All Mark (Note2)
RCLK RCLK RCLK RCLK
RCLK
RPOS RNEG RTIP RRING 0 RTIP RRING 0 RTIP RRING RTIP RRING RTIP RRING 1 RTIP RRING 1 RTIP RRING RTIP RRING
LOS 0 1 0 1 1 1 0 1 0 1 1 1
DFM active active active active active active active active active active active active
0
RCLK
0
RCLK
0
RCLK
0
RCLK
Remote Loopback (RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1)
POL 1 1 1 0 0 0 RDEN * 0 1 * 0 1 TCLK * * * * * * Receive signal clocked loss loss clocked loss loss TTIP TRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING RTIP RRING
RCLK RCLK RCLK 0 RCLK
RCLK
RPOS RNEG RTIP RRING 0 RTIP RRING RTIP RRING 1 RTIP RRING
LOS 0 1 1 0 1 1
DFM active active active active active active
0
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ASAHI KASEI
[AK2540]
Remote Loopback: Transmit all space (RESET=0, AIS=1, AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1)
POL 1 1 1 0 0 0 RDEN * 0 1 * 0 1 TCLK * * * * * * Receive signal clocked loss loss clocked loss loss TTIP TRING 0 0 0 0 0 0
RCLK
RCLK
RPOS RNEG RTIP RRING 0 RTIP RRING RTIP RRING 1 RTIP RRING
LOS 0 1 1 0 1 1
DFM 0 0 0 0 0 0
0 RCLK
RCLK
0
RCLK
Remote Loopback: Transmit all mark (RESET=0, AIS=1, AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1)
POL 1 1 1 0 0 0 RDEN * 0 1 * 0 1 TCLK * * * * * * Receive signal clocked loss loss clocked loss loss TTIP TRING All Mark All Mark All Mark All Mark All Mark All Mark
RCLK
RCLK
RPOS RNEG RTIP RRING 0 RTIP RRING RTIP RRING 1 RTIP RRING
LOS 0 1 1 0 1 1
DFM active active active active active active
0 RCLK
RCLK
0
RCLK
Local Loopback(RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0)
POL 1 1 1 1 0 0 0 0 RDEN * * * * * * * * TCLK clocked clocked loss loss clocked clocked loss loss Receive signal clocked loss clocked loss clocked loss clocked loss TTIP TRING TPOS TNEG TPOS TNEG 0 0 TPOS TNEG TPOS TNEG 0 0 TCLK (Note4) TCLK (Note4) 0/1 (Note3) 0/1 (Note3) TCLK (Note4) TCLK (Note4) 0/1 (Note3) 0/1 (Note3) 0 1 0 TPOS TNEG TPOS TNEG 0 0 0 1 active 0 active 0 1 0 RCLK RPOS RNEG TPOS TNEG TPOS TNEG 0 0 0 1 active 0 active LOS DFM
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ASAHI KASEI
[AK2540]
Local Loopback: Transmit all space (RESET=0, AIS=1, AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0)
POL 1 1 1 1 0 0 0 0 RDEN * * * * * * * * TCLK clocked clocked loss loss clocked clocked loss loss Receive signal clocked loss clocked loss clocked loss clocked loss TTIP TRING 0 0 0 0 0 0 0 0 TCLK (Note4) TCLK (Note4) 0/1 (Note3) 0/1 (Note3) TCLK (Note4) TCLK (Note4) 0/1 (Note3) 0/1 (Note3) 1 1 0 TPOS TNEG TPOS TNEG 1 0 0 1 0 0 0 0 1 0 RCLK RPOS RNEG TPOS TNEG TPOS TNEG 0 0 0 1 0 0 0 LOS DFM
Local Loopback: Transmit all mark (RESET=0, AIS=1, AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0)
POL 1 1 1 1 0 0 0 0 RDEN * * * * * * * * TCLK clocked clocked loss loss clocked clocked loss loss Receive signal clocked loss clocked loss clocked loss clocked loss TTIP TRING All Mark All Mark All Mark (Note2) All Mark (Note2) All Mark All Mark All Mark (Note2) All Mark (Note2) TCLK (Note4) TCLK (Note4) 0/1 (Note3) 0/1 (Note3) TCLK (Note4) TCLK (Note4) 0/1 (Note3) 0/1 (Note3) 1 1 active TPOS TNEG TPOS TNEG 1 0 active 1 active 0 active 0 1 active RCLK RPOS RNEG TPOS TNEG TPOS TNEG 0 0 active 1 active 0 active LOS DFM
Note1) The impedance between TTIP and TRING is 30kohm(typ) Note2) Transmit signal synchronize with MCLK Note3) When CLKE is "1", RCLK is fixed to "1". Note4) The phase of the TCLK satisfy receive output timing.
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ASAHI KASEI RECOMMENDED EXTERNAL CIRCUITS
[AK2540]
Transmit Circuit VDD AK2540 TTIPx VDD C1 1:2 (3.3V) 1:1.14 (5V)
TRINGx C1=0.47F Received Circuit 1:1 (3.3V) 1:0.57 (5V)
AK2540 RTIPx
Rp R1
RRINGx
Rp
R2
R1=R2= 50ohms (3.3V) 154ohms (5V) Rp=100ohms(Protection resistance, Example value)
Recommended Transformer Specification VDD = 3.3V Turns Ratio (Typ) Tx Rx VDD = 5V Turns Ratio (Typ) Tx Rx 1:1.14 1:1.14(CT) Primary Inductance (Min) 1.5mH 1.5mH Leakage Inductance (Max) 0.3uF 0.3uF Interwinding Capacitance (Max) 30pF 30pF DCR (Max) pri 1:2 1:2(CT) Primary Inductance (Min) 1.5mH 1.5mH Leakage Inductance (Max) 0.3uF 0.3uF Interwinding Capacitance (Max) 30pF 30pF DCR (Max) pri
sec
0.6ohms 0.6ohms 0.6ohms 0.6ohms
sec
0.6ohms 0.6ohms 0.6ohms 0.6ohms
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ASAHI KASEI Reference current circuit To determine input reference current, connect 12kohm1% resistor. R1 is recommended to connect to AK2540 as short as possible to avoid noise. AK2540 R1 BGREF
[AK2540]
R1=12kohm1% Power Supply To attenuate the power supply noise, connect capacitors between VDD and VSS respectively. The value of the capacitance AK2540 need depend on the condition of the power supply line. Please decide the value of the capacitance after your evaluation. C1 is recommended to connect to AK2540 as short as possible to avoid noise. AK2540 VDD
C1
Pin name RAVDD-RAVSS, BVDD-BVSS, TAVDD1-TAVSS1, TAVDD2-TAVSS2 TVDD1-TVSS1, IOVDD-IOVSS, TVDD2-TVSS2, DVDD-DVSS, TVDD3-TVSS3, TVDD4-TVSS4, PVDD-PVSS
C1 1uF 0.01uF
Recommended Transformers Selection Power Supply 3.3V Operation 5V Operation Turns Ratio 1:1.14 1:2 Manufacturer TDK Pulse Engineering TDK Pulse Engineering JPC Part Number WBTT-0425B T1104 WBTT-0425 T1105 4101 Description Single, SMT,1.5kV Octal, SMT,1.5kV Single, SMT,1.5kV Octal, SMT,1.5kV Single, SMT,1.5kV
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ASAHI KASEI
[AK2540]
PACKAGE
144pin LQFP Outline Dimensions
22.0 20.0 108 73
109
72
AK2540 XXXXXXX JAPAN
144 37
20.0 36 0.170.040.07
1.70 Max 1.40
1 0.50 0.20
0.10 M
22.0
0 10
0.10
0.10
0.500.1
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